Job?Description-????????Implement?blocks?in?Verilog?RTL-????????Synthesize?and?close?timing?on?the?design-????????Work?closely?with?Design?Verification?team?to?review?strategy,?testplans?and?assist?with?debugs-????????Work?on?code-coverage?analysis,?top-level?connections,?etc.-????????Assist?in?lab?bring-up,?using?logic-analyzer?toolsSkills?Required-????????Ability?to?translate?high-level?functions?into?block?designs-????????Outstanding?coding?and?scripting?skills?(Verilog,?C,?Perl).?SystemVerilog?is?a?plus.-????????Demonstrated?knowledge?in?FPGA/ASIC?physical?aspects?(placement,?routing,?PLL,?I/O,?memories,?etc.)-????????Experience?with?industry?tools?for?synthesis,?timing?analysis-????????Outstanding?written?and?spoken?communication?skills-????????Well?organized?and?Process?oriented-????????Knowledge?of?SSD?is?a?plus-????????Master?degree?is?preferred.-????????At?least?2?years?work?experiences?.
